1. Field of the Invention
This invention relates to a digital PLL (Phase Locked Loop) circuit. More particularly, this invention relates to a digital PLL circuit adapted for use in a receiving part of a relay or a terminal device which receives a burst data signal in a communication network.
2. Description of the Related Art
A digital PLL circuit for generating a clock signal having a frequency which is phase-synchronized with an input signal is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 61-208923.
The circuit comprises a fixed frequency generator, a delay circuit which delays the output signal of the fixed frequency generator to make multiple output signals having a phase difference between each other, a phase changing circuit which selects one of the output signals of the delay circuit, a divider which divides a frequency of the output signal of the phase changing circuit to make an output signal of the whole circuit, a phase comparator which compares the phase of the output signal with the phase of the input signal of the whole circuit, and a phase control pulse generator which controls the phase changing circuit depending on the result of the comparison in the phase comparator.
In the circuit according to the prior art, a considerable lead-in time may be required when receiving a burst signal, because multiple phase comparisons and changes are required to perform phase synchronization if the phase difference between the output signal and the input signal is 180.degree. .